An integrated circuit may contain an N/P configurable extended drain metal oxide semiconductor (MOS) transistor, referred to herein as an N/P MOS transistor, which includes an extended drain n-channel MOS (NMOS) transistor in parallel with an extended drain p-channel MOS (PMOS) transistor. The NMOS transistor and PMOS transistor have drift lanes in their respective extended drains which contact each other along a common length. A drain node of the NMOS transistor is coterminous with a source node of the PMOS transistor, and a source node of the NMOS transistor is coterminous with a drain node of the PMOS transistor. The N/P MOS transistor may be operated in an NMOS mode, in which the NMOS transistor is turned on by applying an on-state bias to an NMOS gate, while the PMOS transistor is turned off, by applying an off-state bias to a PMOS gate. The N/P MOS transistor may also be operated in a PMOS mode, in which the PMOS transistor is turned on by applying an on-state bias to the PMOS gate, while the NMOS transistor is turned off, by applying an off-state bias to the NMOS gate. The N/P MOS transistor may further be operated in a dual mode, in which both the NMOS transistor and the PMOS transistor are turned on by applying the on-state biases to the NMOS gate and to the NMOS gate. A total current through the N/P MOS transistor when operated in the dual mode may be greater than a sum of a current when operated in the NMOS mode and a current when operated in the PMOS mode.
Simulating electronic components and electronic circuits is a staple activity of integrated circuit fabricators. It is desirable to accurately estimate parameters such as current in such simulations. It may thus be desirable to provide a simulation of an N/P MOS transistor which predicts a dual mode total current, an NMOS mode current and a PMOS mode current which accurately reflect measured currents in the N/P MOS transistor being simulated.